The present invention relates to an MOS type semiconductor device such as an IGBT (Insulated Gate Bipolar Transistor), a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor), etc. used as a switching device for power conversion.
Power conversion apparatuses, such as inverter apparatuses, have been applied to various fields in recent years, because there is an accelerated demand for the power conversion apparatuses with advances that meet energy savings requirements due to environmental issues. Application of such power conversion apparatuses has recently advanced to fields particularly requiring high reliability such as electric railroad vehicle engineering, automobile engineering, aeronautical engineering and space engineering. It is a matter of course that a power device used as the key component of this type power conversion apparatus needs to have very high reliability under such circumstances.
On the other hand, it is definitely not easy to produce a faultless and highly reliable device while thoroughly eliminating the influence of minute foreign matter such as outside particles (dirt), particles or dust generated in a production facility, etc. as causes of various device failures and defects in a process of producing a semiconductor device including a power device. It is technically possible to reduce the device failures and defects by improving the cleanliness level of the producing process. Measures to improve the cleanness level, however, are expensive in terms of cost effectiveness.
It is said that a more realistic method to keep a balance between the product cost and the product quality (i.e. to suppress the product cost but not to lower the product quality) is a producing method which permits foreign particles up to a certain degree and which abnormal products consequently produced are screened out in shipping inspection. With respect to the screening, it is easy to discovery defective products and screen out the defective products as rejected products during shipping inspection when the defective products have initial defects exhibiting an abnormal distribution of electric characteristics, etc. There is, however, a possibility that normal products will be damaged or destroyed to reduce the percentage of non-defective products when products are tested for dynamic characteristics, especially, electric characteristics related to device breakdown tolerance. Hence, there is a problem that it is difficult to use the examination of dynamic characteristics as a test item for screening the whole number of products. As a result, there is a possibility that products of low breakdown tolerance will be shipped out.
Typical types of power devices used in such power conversion apparatuses are an IGBT and a power MOSFET. It is known that a typical factor determining the device destruction tolerance of this type device lies in the amplifying function of a parasitic transistor in an MOS structure portion of this type device. For this reason, an IGBT or MOSFET having an n-channel MOS structure is generally designed so that the gain of the parasitic npn transistor is reduced by improvement of a surface pattern or a diffusion profile to make the parasitic npn transistor inactive in an ordinary operation of the IGBT or MOSFET. For example, it is common that a front surface of a p base region is covered with a metal electrode provided in common with an n+ emitter (or n+ source) region to thereby form a short-circuited structure to reduce the gain of the parasitic npn transistor. However, when there is some defect (for example, pattern defect) to increase the gain of the parasitic transistor, the parasitic transistor may be turned on because the potential of the base region of the parasitic transistor increases as an overcurrent flows through the device. If the parasitic transistor is once turned on, there arises a problem that device destruction is brought about by positive feedback in which a temperature rise caused by the current concentrated in the parasitic transistor causes a further current concentration.
This issue will be described specifically based on the background art. FIG. 3A is a plan view showing important part of a trench gate type MOS structure portion of a trench gate type IGBT according to the background art. FIG. 3B is a sectional view taken along the line B-B in FIG. 3A which is a plan view showing the important part. FIG. 3C is a sectional view taken along the line C-C in FIG. 3A. In FIG. 3A which is a plan view showing the important part, a surface electrode pattern of an upper layer is not shown but an interlayer insulating film pattern of a lower layer and a pattern of a further lower layer are shown transparently. In FIG. 3B, a p base region 4 and trenches 5 having a depth extending from a front surface of a substrate to reach an n− drift layer 3 via the p base region 4 are shown on a front surface side of the n− drift layer 3 having an n+ buffer layer 2, a p+ collector layer 1 and a collector electrode 12 on its back surface side. In the following description in this specification, the same term ‘semiconductor substrate’ or ‘substrate’ is used for expressing the substrate as a whole even when the structure of the substrate changes successively in a process of forming functional regions successively on front and back surface sides of the semiconductor substrate input to the process.
The trenches 5 are formed as a pattern of stripes in a surface in the active region where a main current of the trench gate type IGBT flows. In a surface between the striped trenches 5 as a portion where an emitter electrode 8 which will be formed by a post process so as to come into contact with the substrate surface, there are provided an n+ emitter region 9 disposed along the striped trenches 5 so as to be brought into contact with the striped trenches 5 and a p+ contact region 10 formed in parallel to the striped trenches 5 and between the striped trenches 5. As shown in FIGS. 3B and 3C, the n+ emitter region 9, the p base region 4 and the n− drift layer 3 are exposed in a side wall of each trench 5 and each trench 5 is filled with a gate electrode 7 through a gate insulating film 6 formed on the inner surface of the trench 5. When a predetermined gate voltage is applied to each gate electrode 7 under a forward bias between the collector electrode 12 and the emitter electrode 8, an n channel is formed in a surface of the p base region 4 along a side wall of each trench 5 so that a main current flows.
On the other hand, as shown in FIG. 3A, an interlayer insulating film 11 made of BPSG (Boro Phosphor Silicate Glass) or the like is formed on the principal surface side of the semiconductor substrate and an opening is formed in a portion of the interlayer insulating film 11 corresponding to the surface of the n+ emitter region 9 and the surface of the p+ contact region 10 so that the emitter electrode 8 can be brought into contact with the surface of the n+ emitter region 9 and the surface of the p+ contact region 10 as described above. Generally, when a surface pattern in an MOS type power device is formed finely to increase channel density, on-resistance can be reduced to attain improvement of performance. With respect to the degree of fineness to satisfy the performance, it is generally necessary that the width of the opening region of the interlayer insulating film 11 opened to bring the emitter electrode 8 into contact with the surface of the n+ emitter region 9 and the surface of the p+ contact region 10 between the trenches 5 (i.e. the width of the opening region between the trenches 5) is not larger than 1 μm. In this case, the width between the trenches is not larger than about 3 μm. When the width of the contact region between the emitter electrode 8 and the substrate surface is narrow to be not larger than about 1 μm as described above, a method of shaping a surface pattern of the n+ emitter region like a ladder as shown in FIG. 3A without provision of the n+ emitter region 9 and the p+ contact region 10 by subdividing the width of 1 μm is preferably performed in practice to bring the emitter electrode 8 into contact with both the surface of the n+ emitter region 9 and the surface of the p+ contact region 10 stably and surely in consideration of pattern alignment accuracy.
Although the trench gate type IGBT is used in the above description about the surface pattern of the n+ emitter region, the same rule applies to a planar gate type IGBT as shown in FIGS. 5A to 5C. With respect to the fineness of the structure, it is necessary to short-circuit the n+ emitter region 9 to the p+ contact region 10 (p base region 4) by the surface of the minute contact region in the same manner as in the trench gate type IGBT. The same rule applies not only to the IGBT but also to a power MOSFET.
When the surface pattern is made finer as shown in the case where the width between the trenches 5 is not larger than about 3 μm as described above, shaping the surface pattern of the n+ emitter region like a ladder permits the width to be used partially most effectively though the width is small. However, the p+ contact region does not particularly change from the background art even when the surface pattern of the n+ emitter region is shaped like a ladder. Accordingly, the width of the resist decreases as the width of the pattern in the p+ contact region decreases. There is a problem that when adhesive force of the resist is reduced for some reason, the possibility of pattern missing in the p+ contact region will become higher than that in the n+ emitter region. This reason is as follows. When pattern missing occurs in the p+ contact region, contact resistance with the p base region increases partially so that base resistance is apt to increase. Accordingly, the parasitic npn transistor is operated by conduction of a current smaller than the original current value, so that the risk of device breakdown becomes high. Particularly the IGBT is apt to reach device breakdown due to the latch-up of a parasitic thyristor. Therefore, sure inactivation of the parasitic transistor is essential to provision of an MOS type semiconductor device capable of operating reliably and stably.
In view of the above, it would be desirable to provide a reliable MOS type semiconductor device in which increase in the gain of a parasitic transistor caused by photo pattern defects produced easily in accordance with fineness of a process design rule is suppressed to improve breakdown tolerance.